In this work, the hot carrier injection (HCI) induced degradation mechanism of a 20 V silicon-based Lateral Double-Diffused Metal-OxideSemiconductor Field-Effect Transistor (LDMOS) is investigated. A contact field plate (CFP) structure compatible with 0.18 \mu \mathrm~m BCD process is proposed to suppress HCI and enhance the device's HCI reliability. The CFP is positioned atop the drift region to suppress surface electric field spikes, avoid hot electron and hot hole injection into the oxide layer caused by localized high impact ionization, and effectively mitigate the degradation of device electrical parameters. For the proposed low-voltage device, wafer-level HCI degradation tests were performed. Hot carrier injection in the channel region causes charge accumulation in the gate oxide, leading to a positive shift in V_\text th . Experimental results show that V_\text th increases under all stress conditions, and the V_\text th shift becomes more significant at higher V_\mathrmgs. Meanwhile, I_\text dlin decreases gradually; notably, I_\text dlin exhibits a slight positive shift at the initial stress stage under low V_\mathrmgs, followed by a continuous reduction. Sentaurus TCAD was used to analyze the electric field and impact ionization rate, investigate the HCI degradation mechanism, optimize the CFP structure parameters, and verify the performance advantages. Based on experimental data, the hot-carrier degradation mechanism differs under different stress conditions. At low V_\mathrmgs, degradation is dominated by both hot hole injection into the field oxide and hot electron injection into the gate oxide. At high V_\mathrmgs, the influence of hot holes is significantly weakened. With increasing stress time, hot carrier injection gradually saturates, and the generation of interface states ( N_\mathrmit ) becomes the main cause of device degradation.In this work, trap charges were introduced at the \mathrmSi / \mathrmSiO_2 interface in the TCAD simulation to investigate the electrical characteristics of the device before and after hot carrier injection. After optimizing the CFP structure, simulations show that the specific on-resistance ( R_\text on, sp ) degradation rate at hot spots of A and C (within a 0.1 \mu \mathrm~m range, subjected to an injected electron charge of 1 \times 10^9 \mathrm~cm^-2 for 100,000 \mathrm~s ) is reduced by 64.9 \% and 79.4 \%, respectively, compared with the conventional LDMOS. The CFP structure assists the drift region to achieve full depletion, enabling a higher drift region doping concentration while meeting the target breakdown voltage requirement. In terms of fabrication, the CFP etch process is fully compatible with the standard contact etch process in the 0.18 \mu \mathrm~m \mathrmBCD platform, requiring no additional masks or process modifications. Tape-out test results demonstrate that the I_\text din degradation of the CFP LDMOS after 10,000 \mathrm~s of stress is reduced by 62.2 \% relative to the conventional structure, with a breakdown voltage (BV) of 34 V and a R_\mathrmon, \mathrmsp of 6.9 \mathrm~m \Omega \cdot \mathrm~mm^2. The figure of merit (FOM) of the proposed device is approximately 1.6 times that of the conventional structure, demonstrating an excellent trade-off between BV and R_\mathrmon, \mathrmsp alongside superior HCI reliability.