The adder is a core arithmetic component in modern microprocessors, cryptographic circuits, and other systems. Most existing memristor-based full adders adopt the cascaded discrete basic logic gate approach, which leads to large device overhead and long operation steps, making it difficult to meet the requirements of high-speed data processing and real-time encryption. To address these issues, this paper first designs a low-overhead full adder circuit based on the memristor array, which consists of input memristors, output memristors, and an auxiliary memristor. The entire computation is performed within the memristors, using the high-resistance state and low-resistance state to represent logic 0 and logic 1, respectively. Based on Ohm’s law, Kirchhoff’s law, and the full adder truth table, a detailed derivation of the circuit is carried out, and the operating voltages are determined. During computation, specific operating voltages are applied to the bit lines of involved memristors, triggering conditional resistance switching of the output memristor determined by inputs. The proposed full adder requires only six memristors and two operation steps to produce the sum and carry, outperforming existing schemes in both device count and operation efficiency.

Based on the above one-bit full adder, this paper further adopts a one-transistor-one-memristor (1T1M) array to construct an in-memory encryption-decryption circuit. The circuit uses a single-bit full adder as the basic unit to form an encryption-decryption unit (EDU), and an m\times n array of EDUs is integrated to form the encryption-decryption array. For image encryption and decryption applications, two operating modes are developed: 1) Semi-parallel mode: a single column of EDUs is activated at a time to process all pixels in one column of the image in parallel, completing encryption or decryption column by column. Processing an m\times n binary image requires only 2n operation steps. 2) Fully parallel mode: by disconnecting the columns of the array through switches, all columns of EDUs can simultaneously process all columns of pixels, completing the encryption or decryption of the entire image in only 2 steps. Verification using 256\times 256 binary images shows, by comparing the images before and after encryption and decryption, that the proposed encryption-decryption circuit can correctly perform image encryption and decryption.

Finally, this paper proposes a COPY logic operation based on the 1T1M crossbar array, which can copy the resistance state of one memristor to another. By integrating the proposed full adder and COPY gate, an n-bit ripple-carry adder is designed. Specifically, the output carry c_i of the (i-1)-th bit is calculated serially and copied to the memristor at the i-th row of the same column via COPY operation. This serial computation and copying process is iterated until all carries c_i+1 (i = 1, 2, 3,\cdots) are generated. Subsequently, the odd-indexed sums s_i (i = 1, 3, 5,\cdots) and the even-indexed sums s_i (i = 2, 4, 6,\cdots) are computed in parallel, respectively. The complete operation of this n-bit ripple-carry adder requires only 2n+1 operation steps. Compared with existing works, the proposed design achieves improvements of 1.37× to 12.18× in \rm FoM_\mathrmB (equally weighted by step and device count) and 1.80× to 41.98× in \rm FoM_\mathrmS (weighted toward step count), exhibiting distinctly superior overall performance.