This paper deals with the reducing frequency phenomenon in Buck converters with one cycle control. The critical conditions of its occurrance and operation modes are derived. The results show that the reducing frequency phenomenon occurs because the output voltage of the integrator does not rise to the reference voltage Vref within n clock periods so that the integrator can not be reset in n clock periods but must be reset in the (n+1)th clock period. Furthermore, the converters are stable both in CCM and DCM when the reducing frequency phenomenon occurs. Meanwhile, the ratio of the intervals with the reference voltage Vref between CCM and DCM is held constant. In addition, the ripple of the output voltage is increasing with the decrease of the circuit operating frequency. Finally, these theoretical results are verified by the numerical simulation and circuit experiment.