Process optimization and validation of the polysilicon grain-boundary barrier for high-accuracy 3-dimensional NAND compute-in-memory chips

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ZHENG Hao; LIU Huiwen; XU Kezhi; ZHANG Baotong; YANG Yuancheng; XIA Zhiliang; HUO Zongliang

doi:10.7498/aps.75.20260199

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ZHENG Hao, LIU Huiwen, XU Kezhi, ZHANG Baotong, YANG Yuancheng, XIA Zhiliang, HUO Zongliang. Process optimization and validation of the polysilicon grain-boundary barrier for high-accuracy 3-dimensional NAND compute-in-memory chipsJ. Acta Physica Sinica, 2026, 75(8): 080804. DOI: 10.7498/aps.75.20260199

Citation:

ZHENG Hao, LIU Huiwen, XU Kezhi, ZHANG Baotong, YANG Yuancheng, XIA Zhiliang, HUO Zongliang. Process optimization and validation of the polysilicon grain-boundary barrier for high-accuracy 3-dimensional NAND compute-in-memory chipsJ. Acta Physica Sinica, 2026, 75(8): 080804. DOI: 10.7498/aps.75.20260199

Citation:

ZHENG Hao, LIU Huiwen, XU Kezhi, ZHANG Baotong, YANG Yuancheng, XIA Zhiliang, HUO Zongliang. Process optimization and validation of the polysilicon grain-boundary barrier for high-accuracy 3-dimensional NAND compute-in-memory chipsJ. Acta Physica Sinica, 2026, 75(8): 080804. DOI: 10.7498/aps.75.20260199